module div(fast_clock, slow_clock);
	input fast_clock;
	output slow_clock;
	reg slow_clock;
	reg [31:0] num;
	always @(posedge fast_clock)
		begin
			if(num==50000)
				begin
					num <= 0;
					slow_clock <= ~slow_clock;
				end
			else
				num <= num + 1;
		end
endmodule 